1 // Intel Utility Functions
7 #define INTEL_IDX_INST_IN_FPMU 0
8 #define INTEL_IDX_CLK_IN_FPMU 2
11 * REFERENCE CPU MODEL:
12 * Intel Xeon E5620 (family_cpuid: 06_1CH)
13 * Architectural Performance Monitoring Version: 3
14 * Number of general-purpose performance counters: 4
18 #define INTEL_NUM_PMU_COUNTERS 4
19 #define INTEL_NUM_PMU_CONTROLS 4
20 #define INTEL_NUM_FIXED_PMU_COUNTERS 3
21 #define INTEL_NUM_PMU_GLOBAL 3
24 * NOTICE currently there are 7 counters in a total (IA32_PMC0-3 + IA32_FIXED_CTR0-2)
25 * but, only 4 of those are being used if you will
26 * since hard-programmed now for CPI and LLCache Miss Rate are only events that are requested
28 * define NUM_USED_COUNTERS 4 at vmm_pmu.h
32 * MSR OFFSETS FOR PMU RELATED:
35 #define INTEL_IA32_PMC0 0xc1
36 #define INTEL_IA32_PMC1 0xc2
37 #define INTEL_IA32_PMC2 0xc3
38 #define INTEL_IA32_PMC3 0xc4
40 #define INTEL_IA32_PERFEVTSEL0 0x186
41 #define INTEL_IA32_PERFEVTSEL1 0x187
42 #define INTEL_IA32_PERFEVTSEL2 0x188
43 #define INTEL_IA32_PERFEVTSEL3 0x189
46 * 0x309 INTEL_IA32_FIXED_CTR0: counts Instr_Retired.Any
47 * 0x30A INTEL_IA32_FIXED_CTR1: counts CPU_CLK_Unhalted.Core
48 * 0x30B INTEL_IA32_FIXED_CTR2: counts CPU_CLK_Unhalted.Ref
50 #define INTEL_IA32_FIXED_CTR0 0x309
51 #define INTEL_IA32_FIXED_CTR1 0x30a
52 #define INTEL_IA32_FIXED_CTR2 0x30b
54 #define INTEL_IA32_FIXED_CTR_CTRL 0x38d
56 #define INTEL_IA32_PERF_GLOBAL_STATUS 0x38e
57 #define INTEL_IA32_PERF_GLOBAL_CTRL 0x38f
58 #define INTEL_IA32_PERF_GLOBAL_OVF_CTRL 0x390
60 #define INTEL_IA32_PERF_GLOBAL_STATUS_ORDER 0
61 #define INTEL_IA32_PERF_GLOBAL_CTRL_ORDER 1
62 #define INTEL_IA32_PERF_GLOBAL_OVF_CTRL_ORDER 2
64 // bit for relevant configs for PEREVTSEL (perf event selection)
65 #define INTEL_USR_BIT 16
66 #define INTEL_OS_BIT 17
67 #define INTEL_EDGE_BIT 18
68 #define INTEL_PIN_BIT 19
70 #define INTEL_ANY_BIT 21
71 #define INTEL_EN_BIT 22
72 #define INTEL_INV_BIT 23
73 #define INTEL_CMASK_BIT 24
74 #define INTEL_UMASK_BIT 8
75 #define INTEL_EVENT_BIT 0
83 #define INTEL_MSR_OFFSET_PERF(val) (val & 0x3)
85 #define INTEL_CTR_READ(msrs, c) do {rdmsrl((INTEL_IA32_PMC0 + (c)), (msrs).q);} while (0)
86 #define INTEL_CTR_WRITE(msrs, c) do {wrmsrl((INTEL_IA32_PMC0 + (c)), (msrs).q);} while (0)
88 #define INTEL_FIXED_CTR_READ(msrs, c) do {rdmsrl((INTEL_IA32_FIXED_CTR0 + (c)), (msrs).q);} while (0)
89 #define INTEL_FIXED_CTR_WRITE(msrs, c) do {wrmsrl((INTEL_IA32_FIXED_CTR0 + (c)), (msrs).q);} while (0)
91 #define INTEL_CTRL_READ(msrs, c) do {rdmsrl((INTEL_IA32_PERFEVTSEL0 + (c)), (msrs).q);} while (0)
92 #define INTEL_CTRL_WRITE(msrs, c) do {wrmsrl((INTEL_IA32_PERFEVTSEL0 + (c)), (msrs).q);} while (0)
94 // given even and mask, make it to track it on all ring levels
95 #define INTEL_CTRL_START(event, mask, i) \
98 tmp |= (mask)<<INTEL_UMASK_BIT; \
99 tmp |= (event)<<INTEL_EVENT_BIT; \
100 tmp |= 0x3<<INTEL_USR_BIT; \
101 tmp |= 0x1<<INTEL_EN_BIT; \
102 wrmsrl((INTEL_IA32_PERFEVTSEL0 + (i)), tmp); \
103 wrmsrl((INTEL_IA32_PMC0 + (i)), 0x0); \
106 #define INTEL_CTRL_STOP(i) do { wrmsrl((INTEL_IA32_PERFEVTSEL0 + (i)), 0x0); } while(0) \
108 #define INTEL_FIXED_CTRL_READ(msrs) do {rdmsrl(INTEL_IA32_FIXED_CTR_CTRL, (msrs).q);} while (0)
109 #define INTEL_FIXED_CTRL_WRITE(msrs) do {wrmsrl(INTEL_IA32_FIXED_CTR_CTRL, (msrs).q);} while (0)
112 * SELECTED PMU EVENTS AND UMASKS
113 * Intel 64 and IA-32 Arthitectures Software Developer's Manual, Jan 2013
114 * Chap 19 Performance-Monitoring Events
117 // CLK and INSTRUCTIONS events
118 #define INTEL_CLK_NOT_HALTED 0x3C // event
119 #define INTEL_RETIRED_INSTRUCTIONS 0xC0 // event
122 #define INTEL_MEM_INST_RETIRED 0x0B // event
123 #define INTEL_LOADS 0x1 // umask
124 #define INTEL_STORES 0x2 // umask
126 // MEM LOAD events and umasks
127 #define INTEL_MEM_LOAD_RETIRED 0xCB // event
128 #define INTEL_L1D_HIT 0x1 // umask
129 #define INTEL_L2_HIT 0x2 // umask
130 #define INTEL_L3_UNSHARED_HIT 0x4 // umask
131 #define INTEL_OTHER_CORE_L2_HIT_HITM 0x8 // umask
132 #define INTEL_L3_MISS 0x10 // umask
133 #define INTEL_HIT_LFB 0x40 // umask
134 #define INTEL_DTLB_MISS 0x80 // umask