2 * Copyright (c) 2006 Cray, Inc.
4 * The contents of this file is proprietary information of Cray Inc.
5 * and may not be disclosed without prior written consent.
9 * This code is licensed under the GNU General Public License,
10 * Version 2. See the file COPYING for more details.
14 #ifndef __L0RCA_CONFIG_H__
15 #define __L0RCA_CONFIG_H__
18 #include <rca/cray_event_def.h> /* rca_types.h includes rs_event.h */
21 * PKT_MODE* Registers:
23 * Writing a "0" to a bit in pkt_mode0 will atomically clear that bit
24 * in pkt_mode. Writing a "1" to a bit in pkt_mode1 will atomically
25 * set that bit in pkt_mode. Reading any of these will return the
26 * instantanious contents of pkt_mode. Writing pkt_mode replaces the
27 * contents non-atomically.
32 uint32_t pkt_mode0; /* atomically clear bits */
34 uint32_t pkt_mode1; /* atomically set bits */
37 #define phy_pkt_mode (*(l0ssi_pkt_mode_t *)PKT_MODE)
39 #define PKT_MODE0 (uint32_t)&phy_pkt_mode.pkt_mode0
40 #define PKT_MODE1 (uint32_t)&phy_pkt_mode.pkt_mode1
43 * How the RCA interrupts the L0.
45 * Writing a "0" to a bit in pkt_mode0 will atomically CLEAR that bit
46 * in pkt_mode. Writing a "1" to a bit in pkt_mode1 will atomically
47 * SET that bit in pkt_mode. Normally, pkt_mode should never be
48 * written directly. It can be read to get the current state of bits.
49 * In general, any set bits in pkt_mode will cause an interrupt to
50 * be raised to the L0, via the SSI and L0_FPGA.
52 * CAUTION: pkt_mode0 must only be written with "0"(s) in the
53 * position(s) to be cleared and "1"s everywhere else. I.e. it
54 * must be written with the value one would use to AND-out the
55 * bits. This is contrary to most SET/CLEAR register implementations.
57 * Bits in pkt_mode are assigned in l0ssi_intr.h
59 typedef l0ssi_pkt_mode_t l0rca_intr_t;
60 #define l0r_intr_get pkt_mode
61 #define l0r_intr_clr pkt_mode0
62 #define l0r_intr_set pkt_mode1
64 /* Should be removed... */
65 #define L0RCA_CONFIG L0RCA_CFG
67 /* defined channel id */
68 #define L0RCA_CH_EV_UP 0
69 #define L0RCA_CH_EV_DOWN 1
70 #define L0RCA_CH_CON_UP 2
71 #define L0RCA_CH_CON_DOWN 3
72 #define L0RCA_CH_KGDB_UP 4
73 #define L0RCA_CH_KGDB_DOWN 5
74 #define NUM_L0RCA_CHANNELS 6
76 /* NOTE for the following L0 Opteron communication related structures:
77 * ###################################################################
78 * There are following restrictions for the L0 Opteron communication
80 * The elements must be aligned on 4-byte boundaries. The structure
81 * size must be a multiple of 4 bytes. Structures should be packed so
82 * that the compiler will not insert padding.
83 * ###################################################################
87 * l0rca_ch_data_t: channel buffer data structure
88 * NOTE: This l0rca_ch_data_t is packed. If we update this structure,
89 * we need to make sure that each element is 4-byte aligned,
90 * otherwise it might break the L0 Opteron communication (size of
91 * l0rca_ch_data_t must be a multiple of 4bytes).
92 * All communication channel uses rs_event_t so, the size of object
93 * in buffer is sizeof(rs_event_t). RCA events has fixed ev_data
94 * length (256) and num_obj is the number of events can be stored
97 * The *_intr_bit fields declare which bit in the PKT_MODE register
98 * is used for the channel interrupt. l0_intr_bit is for interrupts
99 * sent *to* the L0, while proc_intr_bit is for interrupts sent *to*
100 * the Opteron processor.
102 typedef struct l0rca_ch_data_s {
103 uint32_t num_obj; /* number of objects */
104 uint32_t ridx; /* read index */
105 uint32_t widx; /* write index */
106 uint32_t l0_intr_bit; /* Opteron -> L0 intr assignment */
107 uint32_t proc_intr_bit; /* L0 -> Opteron intr assignment */
108 } __attribute__((packed)) l0rca_ch_data_t;
110 #define L0RCA_CONF_VERSION 2
113 * Circular Buffer Usage:
115 * When (widx == ridx), buffer is empty;
116 * ELSE When (widx - ridx < num_obj)), there are one or more
119 * ridx and widx reflect the object index, not byte index.
123 * num_obj must be a power of 2 (i.e. (num_obj & (num_obj - 1)) == 0).
124 * Therefore indices are normalized with AND: idx = ridx & (num_obj - 1).
129 * NOTE: This l0rca_config_t is packed. If we update this sturcture,
130 * we need to make sure that each element is 4-byte aligned,
131 * otherwise it might break the L0 Opteron communication (size
132 * of l0rca_config_t must be a multiple of 4bytes).
134 * configuration data structure */
135 typedef struct l0rca_config_s {
136 uint64_t l0rca_buf_addr; /* ch buffer addr */
137 uint64_t l0rca_l0_intr_addr; /* interrupt to L0 */
138 uint32_t version; /* config version */
139 rs_node_t proc_id; /* node id */
140 int32_t proc_num; /* proc number (0-3) */
141 int32_t reserved_1; /* reserved for future use */
142 int32_t reserved_2; /* reserved for future use */
144 l0rca_ch_data_t chnl_data[NUM_L0RCA_CHANNELS];
145 } __attribute__((packed)) l0rca_config_t;
149 * Definitions in the L0-reserved area of SIC RAM
151 #define L0_SIC_RAM 0xfffff000
152 #define L0_SIC_RAM_LEN 4096
154 #define COLDSPIN 0xfffffe80
155 #define L0RCA_CFG L0_SIC_RAM
156 #define L0RCA_CFG_LEN (COLDSPIN - L0RCA_CFG)
159 * The following provides an abstraction for accessing the RAM
160 * location of the config structure. It set phy_l0r_cfg to the
161 * l0rca_config_t physical address defined as L0RCA_CONFIG.
162 * To use it, include this header file and then access the
163 * config area as &phy_l0r_cfg.<element>.
165 #define phy_l0r_cfg (*(l0rca_config_t *)L0RCA_CFG)
168 #endif /* !__L0RCA_CONFIG_H__ */