3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "ioport.h" // outb
9 #include "farptr.h" // SET_FARVAR
10 #include "biosvar.h" // GET_BDA
11 #include "vgatables.h" // VGAREG_*
14 // * replace direct in/out calls with wrapper functions
17 /****************************************************************
19 ****************************************************************/
22 vgahw_screen_disable(void)
24 inb(VGAREG_ACTL_RESET);
25 outb(0x00, VGAREG_ACTL_ADDRESS);
29 vgahw_screen_enable(void)
31 inb(VGAREG_ACTL_RESET);
32 outb(0x20, VGAREG_ACTL_ADDRESS);
36 vgahw_set_border_color(u8 color)
38 inb(VGAREG_ACTL_RESET);
39 outb(0x00, VGAREG_ACTL_ADDRESS);
43 outb(v1, VGAREG_ACTL_WRITE_DATA);
47 for (i = 1; i < 4; i++) {
48 outb(i, VGAREG_ACTL_ADDRESS);
50 u8 cur = inb(VGAREG_ACTL_READ_DATA);
53 outb(cur, VGAREG_ACTL_WRITE_DATA);
55 outb(0x20, VGAREG_ACTL_ADDRESS);
59 vgahw_set_overscan_border_color(u8 color)
61 inb(VGAREG_ACTL_RESET);
62 outb(0x11, VGAREG_ACTL_ADDRESS);
63 outb(color, VGAREG_ACTL_WRITE_DATA);
64 outb(0x20, VGAREG_ACTL_ADDRESS);
68 vgahw_get_overscan_border_color(void)
70 inb(VGAREG_ACTL_RESET);
71 outb(0x11, VGAREG_ACTL_ADDRESS);
72 u8 v = inb(VGAREG_ACTL_READ_DATA);
73 inb(VGAREG_ACTL_RESET);
74 outb(0x20, VGAREG_ACTL_ADDRESS);
79 vgahw_set_palette(u8 palid)
81 inb(VGAREG_ACTL_RESET);
84 for (i = 1; i < 4; i++) {
85 outb(i, VGAREG_ACTL_ADDRESS);
87 u8 v = inb(VGAREG_ACTL_READ_DATA);
90 outb(v, VGAREG_ACTL_WRITE_DATA);
92 outb(0x20, VGAREG_ACTL_ADDRESS);
96 vgahw_set_single_palette_reg(u8 reg, u8 val)
98 inb(VGAREG_ACTL_RESET);
99 outb(reg, VGAREG_ACTL_ADDRESS);
100 outb(val, VGAREG_ACTL_WRITE_DATA);
101 outb(0x20, VGAREG_ACTL_ADDRESS);
105 vgahw_get_single_palette_reg(u8 reg)
107 inb(VGAREG_ACTL_RESET);
108 outb(reg, VGAREG_ACTL_ADDRESS);
109 u8 v = inb(VGAREG_ACTL_READ_DATA);
110 inb(VGAREG_ACTL_RESET);
111 outb(0x20, VGAREG_ACTL_ADDRESS);
116 vgahw_set_all_palette_reg(u16 seg, u8 *data_far)
118 inb(VGAREG_ACTL_RESET);
120 for (i = 0; i < 0x10; i++) {
121 outb(i, VGAREG_ACTL_ADDRESS);
122 u8 val = GET_FARVAR(seg, *data_far);
123 outb(val, VGAREG_ACTL_WRITE_DATA);
126 outb(0x11, VGAREG_ACTL_ADDRESS);
127 outb(GET_FARVAR(seg, *data_far), VGAREG_ACTL_WRITE_DATA);
128 outb(0x20, VGAREG_ACTL_ADDRESS);
132 vgahw_get_all_palette_reg(u16 seg, u8 *data_far)
135 for (i = 0; i < 0x10; i++) {
136 inb(VGAREG_ACTL_RESET);
137 outb(i, VGAREG_ACTL_ADDRESS);
138 SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
141 inb(VGAREG_ACTL_RESET);
142 outb(0x11, VGAREG_ACTL_ADDRESS);
143 SET_FARVAR(seg, *data_far, inb(VGAREG_ACTL_READ_DATA));
144 inb(VGAREG_ACTL_RESET);
145 outb(0x20, VGAREG_ACTL_ADDRESS);
149 vgahw_toggle_intensity(u8 flag)
151 inb(VGAREG_ACTL_RESET);
152 outb(0x10, VGAREG_ACTL_ADDRESS);
153 u8 val = (inb(VGAREG_ACTL_READ_DATA) & 0xf7) | ((flag & 0x01) << 3);
154 outb(val, VGAREG_ACTL_WRITE_DATA);
155 outb(0x20, VGAREG_ACTL_ADDRESS);
159 vgahw_select_video_dac_color_page(u8 flag, u8 data)
161 inb(VGAREG_ACTL_RESET);
162 outb(0x10, VGAREG_ACTL_ADDRESS);
163 u8 val = inb(VGAREG_ACTL_READ_DATA);
164 if (!(flag & 0x01)) {
165 // select paging mode
166 val = (val & 0x7f) | (data << 7);
167 outb(val, VGAREG_ACTL_WRITE_DATA);
168 outb(0x20, VGAREG_ACTL_ADDRESS);
172 inb(VGAREG_ACTL_RESET);
173 outb(0x14, VGAREG_ACTL_ADDRESS);
177 outb(data, VGAREG_ACTL_WRITE_DATA);
178 outb(0x20, VGAREG_ACTL_ADDRESS);
182 vgahw_read_video_dac_state(u8 *pmode, u8 *curpage)
184 inb(VGAREG_ACTL_RESET);
185 outb(0x10, VGAREG_ACTL_ADDRESS);
186 u8 val1 = inb(VGAREG_ACTL_READ_DATA) >> 7;
188 inb(VGAREG_ACTL_RESET);
189 outb(0x14, VGAREG_ACTL_ADDRESS);
190 u8 val2 = inb(VGAREG_ACTL_READ_DATA) & 0x0f;
194 inb(VGAREG_ACTL_RESET);
195 outb(0x20, VGAREG_ACTL_ADDRESS);
202 /****************************************************************
204 ****************************************************************/
207 vgahw_set_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
209 outb(start, VGAREG_DAC_WRITE_ADDRESS);
211 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
213 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
215 outb(GET_FARVAR(seg, *data_far), VGAREG_DAC_DATA);
222 vgahw_get_dac_regs(u16 seg, u8 *data_far, u8 start, int count)
224 outb(start, VGAREG_DAC_READ_ADDRESS);
226 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
228 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
230 SET_FARVAR(seg, *data_far, inb(VGAREG_DAC_DATA));
237 vgahw_set_pel_mask(u8 val)
239 outb(val, VGAREG_PEL_MASK);
243 vgahw_get_pel_mask(void)
245 return inb(VGAREG_PEL_MASK);
249 vgahw_save_dac_state(u16 seg, struct saveDACcolors *info)
251 /* XXX: check this */
252 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
253 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
254 SET_FARVAR(seg, info->pelmask, inb(VGAREG_PEL_MASK));
255 vgahw_get_dac_regs(seg, info->dac, 0, 256);
256 SET_FARVAR(seg, info->color_select, 0);
260 vgahw_restore_dac_state(u16 seg, struct saveDACcolors *info)
262 outb(GET_FARVAR(seg, info->pelmask), VGAREG_PEL_MASK);
263 vgahw_set_dac_regs(seg, info->dac, 0, 256);
264 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
268 /****************************************************************
270 ****************************************************************/
273 vgahw_sequ_write(u8 index, u8 value)
275 outw((value<<8) | index, VGAREG_SEQU_ADDRESS);
279 vgahw_grdc_write(u8 index, u8 value)
281 outw((value<<8) | index, VGAREG_GRDC_ADDRESS);
285 vgahw_set_text_block_specifier(u8 spec)
287 outw((spec << 8) | 0x03, VGAREG_SEQU_ADDRESS);
291 get_font_access(void)
293 outw(0x0100, VGAREG_SEQU_ADDRESS);
294 outw(0x0402, VGAREG_SEQU_ADDRESS);
295 outw(0x0704, VGAREG_SEQU_ADDRESS);
296 outw(0x0300, VGAREG_SEQU_ADDRESS);
297 outw(0x0204, VGAREG_GRDC_ADDRESS);
298 outw(0x0005, VGAREG_GRDC_ADDRESS);
299 outw(0x0406, VGAREG_GRDC_ADDRESS);
303 release_font_access(void)
305 outw(0x0100, VGAREG_SEQU_ADDRESS);
306 outw(0x0302, VGAREG_SEQU_ADDRESS);
307 outw(0x0304, VGAREG_SEQU_ADDRESS);
308 outw(0x0300, VGAREG_SEQU_ADDRESS);
309 u16 v = (inw(VGAREG_READ_MISC_OUTPUT) & 0x01) ? 0x0e : 0x0a;
310 outw((v << 8) | 0x06, VGAREG_GRDC_ADDRESS);
311 outw(0x0004, VGAREG_GRDC_ADDRESS);
312 outw(0x1005, VGAREG_GRDC_ADDRESS);
316 /****************************************************************
318 ****************************************************************/
323 return GET_BDA(crtc_address);
327 vgahw_set_cursor_shape(u8 start, u8 end)
329 u16 crtc_addr = get_crtc();
330 outb(0x0a, crtc_addr);
331 outb(start, crtc_addr + 1);
332 outb(0x0b, crtc_addr);
333 outb(end, crtc_addr + 1);
337 vgahw_set_active_page(u16 address)
339 u16 crtc_addr = get_crtc();
340 outb(0x0c, crtc_addr);
341 outb((address & 0xff00) >> 8, crtc_addr + 1);
342 outb(0x0d, crtc_addr);
343 outb(address & 0x00ff, crtc_addr + 1);
347 vgahw_set_cursor_pos(u16 address)
349 u16 crtc_addr = get_crtc();
350 outb(0x0e, crtc_addr);
351 outb((address & 0xff00) >> 8, crtc_addr + 1);
352 outb(0x0f, crtc_addr);
353 outb(address & 0x00ff, crtc_addr + 1);
357 vgahw_set_scan_lines(u8 lines)
359 u16 crtc_addr = get_crtc();
360 outb(0x09, crtc_addr);
361 u8 crtc_r9 = inb(crtc_addr + 1);
362 crtc_r9 = (crtc_r9 & 0xe0) | (lines - 1);
363 outb(crtc_r9, crtc_addr + 1);
366 // Get vertical display end
370 u16 crtc_addr = get_crtc();
371 outb(0x12, crtc_addr);
372 u16 vde = inb(crtc_addr + 1);
373 outb(0x07, crtc_addr);
374 u8 ovl = inb(crtc_addr + 1);
375 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
380 /****************************************************************
381 * Save/Restore/Set state
382 ****************************************************************/
385 vgahw_save_state(u16 seg, struct saveVideoHardware *info)
387 u16 crtc_addr = get_crtc();
388 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
389 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
390 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
391 inb(VGAREG_ACTL_RESET);
392 u16 ar_index = inb(VGAREG_ACTL_ADDRESS);
393 SET_FARVAR(seg, info->actl_index, ar_index);
394 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
397 for (i=0; i<4; i++) {
398 outb(i+1, VGAREG_SEQU_ADDRESS);
399 SET_FARVAR(seg, info->sequ_regs[i], inb(VGAREG_SEQU_DATA));
401 outb(0, VGAREG_SEQU_ADDRESS);
402 SET_FARVAR(seg, info->sequ0, inb(VGAREG_SEQU_DATA));
404 for (i=0; i<25; i++) {
406 SET_FARVAR(seg, info->crtc_regs[i], inb(crtc_addr + 1));
409 for (i=0; i<20; i++) {
410 inb(VGAREG_ACTL_RESET);
411 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
412 SET_FARVAR(seg, info->actl_regs[i], inb(VGAREG_ACTL_READ_DATA));
414 inb(VGAREG_ACTL_RESET);
416 for (i=0; i<9; i++) {
417 outb(i, VGAREG_GRDC_ADDRESS);
418 SET_FARVAR(seg, info->grdc_regs[i], inb(VGAREG_GRDC_DATA));
421 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
423 /* XXX: read plane latches */
425 SET_FARVAR(seg, info->plane_latch[i], 0);
429 vgahw_restore_state(u16 seg, struct saveVideoHardware *info)
431 // Reset Attribute Ctl flip-flop
432 inb(VGAREG_ACTL_RESET);
434 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
437 for (i=0; i<4; i++) {
438 outb(i+1, VGAREG_SEQU_ADDRESS);
439 outb(GET_FARVAR(seg, info->sequ_regs[i]), VGAREG_SEQU_DATA);
441 outb(0, VGAREG_SEQU_ADDRESS);
442 outb(GET_FARVAR(seg, info->sequ0), VGAREG_SEQU_DATA);
444 // Disable CRTC write protection
445 outw(0x0011, crtc_addr);
450 outb(GET_FARVAR(seg, info->crtc_regs[i]), crtc_addr + 1);
452 // select crtc base address
453 u16 v = inb(VGAREG_READ_MISC_OUTPUT) & ~0x01;
454 if (crtc_addr == VGAREG_VGA_CRTC_ADDRESS)
456 outb(v, VGAREG_WRITE_MISC_OUTPUT);
458 // enable write protection if needed
459 outb(0x11, crtc_addr);
460 outb(GET_FARVAR(seg, info->crtc_regs[0x11]), crtc_addr + 1);
463 u16 ar_index = GET_FARVAR(seg, info->actl_index);
464 inb(VGAREG_ACTL_RESET);
465 for (i=0; i<20; i++) {
466 outb(i | (ar_index & 0x20), VGAREG_ACTL_ADDRESS);
467 outb(GET_FARVAR(seg, info->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
469 outb(ar_index, VGAREG_ACTL_ADDRESS);
470 inb(VGAREG_ACTL_RESET);
472 for (i=0; i<9; i++) {
473 outb(i, VGAREG_GRDC_ADDRESS);
474 outb(GET_FARVAR(seg, info->grdc_regs[i]), VGAREG_GRDC_DATA);
477 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
478 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
479 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
480 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
484 vgahw_set_mode(struct VideoParam_s *vparam_g)
486 // Reset Attribute Ctl flip-flop
487 inb(VGAREG_ACTL_RESET);
491 for (i = 0; i <= 0x13; i++) {
492 outb(i, VGAREG_ACTL_ADDRESS);
493 outb(GET_GLOBAL(vparam_g->actl_regs[i]), VGAREG_ACTL_WRITE_DATA);
495 outb(0x14, VGAREG_ACTL_ADDRESS);
496 outb(0x00, VGAREG_ACTL_WRITE_DATA);
499 outb(0, VGAREG_SEQU_ADDRESS);
500 outb(0x03, VGAREG_SEQU_DATA);
501 for (i = 1; i <= 4; i++) {
502 outb(i, VGAREG_SEQU_ADDRESS);
503 outb(GET_GLOBAL(vparam_g->sequ_regs[i - 1]), VGAREG_SEQU_DATA);
507 for (i = 0; i <= 8; i++) {
508 outb(i, VGAREG_GRDC_ADDRESS);
509 outb(GET_GLOBAL(vparam_g->grdc_regs[i]), VGAREG_GRDC_DATA);
512 // Set CRTC address VGA or MDA
513 u8 miscreg = GET_GLOBAL(vparam_g->miscreg);
514 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
516 crtc_addr = VGAREG_MDA_CRTC_ADDRESS;
518 // Disable CRTC write protection
519 outw(0x0011, crtc_addr);
521 for (i = 0; i <= 0x18; i++) {
523 outb(GET_GLOBAL(vparam_g->crtc_regs[i]), crtc_addr + 1);
526 // Set the misc register
527 outb(miscreg, VGAREG_WRITE_MISC_OUTPUT);
530 outb(0x20, VGAREG_ACTL_ADDRESS);
531 inb(VGAREG_ACTL_RESET);
535 /****************************************************************
537 ****************************************************************/
540 vgahw_enable_video_addressing(u8 disable)
542 u8 v = (disable & 1) ? 0x00 : 0x02;
543 u8 v2 = inb(VGAREG_READ_MISC_OUTPUT) & ~0x02;
544 outb(v | v2, VGAREG_WRITE_MISC_OUTPUT);
550 // switch to color mode and enable CPU access 480 lines
551 outb(0xc3, VGAREG_WRITE_MISC_OUTPUT);
552 // more than 64k 3C4/04
553 outb(0x04, VGAREG_SEQU_ADDRESS);
554 outb(0x02, VGAREG_SEQU_DATA);