1 // QEMU Cirrus CLGD 54xx VGABIOS Extension.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (c) 2004 Makoto Suzuki (suzu)
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "vgatables.h" // cirrus_init
9 #include "biosvar.h" // GET_GLOBAL
10 #include "util.h" // dprintf
12 struct cirrus_mode_s {
19 u16 hidden_dac; /* 0x3c6 */
21 u16 *graph; /* 0x3ce */
22 u16 *crtc; /* 0x3d4 */
38 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
39 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
40 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
43 static u16 cgraph_svgacolor[] VAR16 = {
44 0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
49 static u16 cseq_640x480x8[] VAR16 = {
50 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
51 0x580b,0x580c,0x580d,0x580e,
53 0x331b,0x331c,0x331d,0x331e,
56 static u16 ccrtc_640x480x8[] VAR16 = {
58 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
60 0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
65 static u16 cseq_640x480x16[] VAR16 = {
66 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
67 0x580b,0x580c,0x580d,0x580e,
69 0x331b,0x331c,0x331d,0x331e,
72 static u16 ccrtc_640x480x16[] VAR16 = {
74 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
76 0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
81 static u16 cseq_640x480x24[] VAR16 = {
82 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
83 0x580b,0x580c,0x580d,0x580e,
85 0x331b,0x331c,0x331d,0x331e,
88 static u16 ccrtc_640x480x24[] VAR16 = {
90 0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
92 0xea10,0xdf12,0x0013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
97 static u16 cseq_800x600x8[] VAR16 = {
98 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
99 0x230b,0x230c,0x230d,0x230e,
100 0x0412,0x0013,0x2017,
101 0x141b,0x141c,0x141d,0x141e,
104 static u16 ccrtc_800x600x8[] VAR16 = {
105 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
106 0x6009,0x000c,0x000d,
107 0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
108 0x001a,0x221b,0x001d,
112 static u16 cseq_800x600x16[] VAR16 = {
113 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
114 0x230b,0x230c,0x230d,0x230e,
115 0x0412,0x0013,0x2017,
116 0x141b,0x141c,0x141d,0x141e,
119 static u16 ccrtc_800x600x16[] VAR16 = {
120 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
121 0x6009,0x000c,0x000d,
122 0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
123 0x001a,0x221b,0x001d,
127 static u16 cseq_800x600x24[] VAR16 = {
128 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
129 0x230b,0x230c,0x230d,0x230e,
130 0x0412,0x0013,0x2017,
131 0x141b,0x141c,0x141d,0x141e,
134 static u16 ccrtc_800x600x24[] VAR16 = {
135 0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
136 0x6009,0x000c,0x000d,
137 0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
138 0x001a,0x321b,0x001d,
142 static u16 cseq_1024x768x8[] VAR16 = {
143 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
144 0x760b,0x760c,0x760d,0x760e,
145 0x0412,0x0013,0x2017,
146 0x341b,0x341c,0x341d,0x341e,
149 static u16 ccrtc_1024x768x8[] VAR16 = {
150 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
151 0x6009,0x000c,0x000d,
152 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
153 0x001a,0x221b,0x001d,
157 static u16 cseq_1024x768x16[] VAR16 = {
158 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
159 0x760b,0x760c,0x760d,0x760e,
160 0x0412,0x0013,0x2017,
161 0x341b,0x341c,0x341d,0x341e,
164 static u16 ccrtc_1024x768x16[] VAR16 = {
165 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
166 0x6009,0x000c,0x000d,
167 0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
168 0x001a,0x321b,0x001d,
172 static u16 cseq_1024x768x24[] VAR16 = {
173 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
174 0x760b,0x760c,0x760d,0x760e,
175 0x0412,0x0013,0x2017,
176 0x341b,0x341c,0x341d,0x341e,
179 static u16 ccrtc_1024x768x24[] VAR16 = {
180 0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
181 0x6009,0x000c,0x000d,
182 0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
183 0x001a,0x321b,0x001d,
187 static u16 cseq_1280x1024x8[] VAR16 = {
188 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
189 0x760b,0x760c,0x760d,0x760e,
190 0x0412,0x0013,0x2017,
191 0x341b,0x341c,0x341d,0x341e,
194 static u16 ccrtc_1280x1024x8[] VAR16 = {
195 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
196 0x6009,0x000c,0x000d,
197 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
198 0x001a,0x221b,0x001d,
202 static u16 cseq_1280x1024x16[] VAR16 = {
203 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
204 0x760b,0x760c,0x760d,0x760e,
205 0x0412,0x0013,0x2017,
206 0x341b,0x341c,0x341d,0x341e,
209 static u16 ccrtc_1280x1024x16[] VAR16 = {
210 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
211 0x6009,0x000c,0x000d,
212 0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
213 0x001a,0x321b,0x001d,
218 static u16 cseq_1600x1200x8[] VAR16 = {
219 0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
220 0x760b,0x760c,0x760d,0x760e,
221 0x0412,0x0013,0x2017,
222 0x341b,0x341c,0x341d,0x341e,
225 static u16 ccrtc_1600x1200x8[] VAR16 = {
226 0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
227 0x6009,0x000c,0x000d,
228 0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
229 0x001a,0x221b,0x001d,
233 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
234 {0x5f,640,480,8,0x00,
235 cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8,8,
237 {0x64,640,480,16,0xe1,
238 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
240 {0x66,640,480,15,0xf0,
241 cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16,16,
242 6,5,10,5,5,5,0,1,15},
243 {0x71,640,480,24,0xe5,
244 cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24,24,
247 {0x5c,800,600,8,0x00,
248 cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8,8,
250 {0x65,800,600,16,0xe1,
251 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
253 {0x67,800,600,15,0xf0,
254 cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16,16,
255 6,5,10,5,5,5,0,1,15},
257 {0x60,1024,768,8,0x00,
258 cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8,8,
260 {0x74,1024,768,16,0xe1,
261 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
263 {0x68,1024,768,15,0xf0,
264 cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16,16,
265 6,5,10,5,5,5,0,1,15},
267 {0x78,800,600,24,0xe5,
268 cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24,24,
270 {0x79,1024,768,24,0xe5,
271 cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24,24,
274 {0x6d,1280,1024,8,0x00,
275 cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8,8,
277 {0x69,1280,1024,15,0xf0,
278 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
279 6,5,10,5,5,5,0,1,15},
280 {0x75,1280,1024,16,0xe1,
281 cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16,16,
284 {0x7b,1600,1200,8,0x00,
285 cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8,8,
288 {0xfe,0,0,0,0,cseq_vga,cgraph_vga,ccrtc_vga,0,
289 0xff,0,0,0,0,0,0,0,0},
292 static struct cirrus_mode_s *
293 cirrus_get_modeentry(u8 mode)
295 struct cirrus_mode_s *table_g = cirrus_modes;
296 while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
297 u16 tmode = GET_GLOBAL(table_g->mode);
306 cirrus_switch_mode_setregs(u16 *data, u16 port)
309 u16 val = GET_GLOBAL(*data);
318 cirrus_get_crtc(void)
320 if (inb(VGAREG_READ_MISC_OUTPUT) & 1)
321 return VGAREG_VGA_CRTC_ADDRESS;
322 return VGAREG_MDA_CRTC_ADDRESS;
326 cirrus_switch_mode(struct cirrus_mode_s *table)
328 // Unlock cirrus special
329 outw(0x1206, VGAREG_SEQU_ADDRESS);
330 cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
331 cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
332 cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), cirrus_get_crtc());
334 outb(0x00, VGAREG_PEL_MASK);
335 inb(VGAREG_PEL_MASK);
336 inb(VGAREG_PEL_MASK);
337 inb(VGAREG_PEL_MASK);
338 inb(VGAREG_PEL_MASK);
339 outb(GET_GLOBAL(table->hidden_dac), VGAREG_PEL_MASK);
340 outb(0xff, VGAREG_PEL_MASK);
342 u8 vesacolortype = GET_GLOBAL(table->vesacolortype);
343 u8 v = vgahw_get_single_palette_reg(0x10) & 0xfe;
344 if (vesacolortype == 3)
346 else if (vesacolortype)
348 vgahw_set_single_palette_reg(0x10, v);
352 cirrus_set_video_mode(u8 mode)
354 dprintf(1, "cirrus mode %d\n", mode);
355 SET_BDA(vbe_mode, 0);
356 struct cirrus_mode_s *table_g = cirrus_get_modeentry(mode & 0x7f);
358 //XXX - cirrus_set_video_mode_extended(table);
361 table_g = cirrus_get_modeentry(0xfe);
362 cirrus_switch_mode(table_g);
363 dprintf(1, "cirrus mode switch regular\n");
369 outw(0x9206, VGAREG_SEQU_ADDRESS);
370 return inb(VGAREG_SEQU_DATA) == 0x12;
376 dprintf(1, "cirrus init\n");
377 if (! cirrus_check())
379 dprintf(1, "cirrus init 2\n");
382 outb(0x0f, VGAREG_SEQU_ADDRESS);
383 u8 v = inb(VGAREG_SEQU_DATA);
384 outb(((v & 0x18) << 8) | 0x0a, VGAREG_SEQU_ADDRESS);
386 outw(0x0007, VGAREG_SEQU_ADDRESS);
388 outw(0x0431, VGAREG_GRDC_ADDRESS);
389 outw(0x0031, VGAREG_GRDC_ADDRESS);