5 int ehci_init(struct pci_device *pci, int busid, struct pci_device *comppci);
7 void ehci_free_pipe(struct usb_pipe *p);
8 struct usb_pipe *ehci_alloc_control_pipe(struct usb_pipe *dummy);
9 int ehci_control(struct usb_pipe *p, int dir, const void *cmd, int cmdsize
10 , void *data, int datasize);
11 struct usb_pipe *ehci_alloc_bulk_pipe(struct usb_pipe *dummy);
12 int ehci_send_bulk(struct usb_pipe *p, int dir, void *data, int datasize);
13 struct usb_pipe *ehci_alloc_intr_pipe(struct usb_pipe *dummy, int frameexp);
14 int ehci_poll_intr(struct usb_pipe *p, void *data);
17 /****************************************************************
18 * ehci structs and flags
19 ****************************************************************/
30 #define HCC_64BIT_ADDR 1
32 #define HCS_N_PORTS_MASK 0xf
47 #define CMD_PARK (1<<11)
48 #define CMD_PARK_CNT(c) (((c)>>8)&3)
49 #define CMD_LRESET (1<<7)
50 #define CMD_IAAD (1<<6)
51 #define CMD_ASE (1<<5)
52 #define CMD_PSE (1<<4)
53 #define CMD_HCRESET (1<<1)
54 #define CMD_RUN (1<<0)
56 #define STS_ASS (1<<15)
57 #define STS_PSS (1<<14)
58 #define STS_RECL (1<<13)
59 #define STS_HALT (1<<12)
60 #define STS_IAA (1<<5)
61 #define STS_FATAL (1<<4)
62 #define STS_FLR (1<<3)
63 #define STS_PCD (1<<2)
64 #define STS_ERR (1<<1)
65 #define STS_INT (1<<0)
67 #define FLAG_CF (1<<0)
69 #define PORT_WKOC_E (1<<22)
70 #define PORT_WKDISC_E (1<<21)
71 #define PORT_WKCONN_E (1<<20)
72 #define PORT_TEST_PKT (0x4<<16)
73 #define PORT_LED_OFF (0<<14)
74 #define PORT_LED_AMBER (1<<14)
75 #define PORT_LED_GREEN (2<<14)
76 #define PORT_LED_MASK (3<<14)
77 #define PORT_OWNER (1<<13)
78 #define PORT_POWER (1<<12)
79 #define PORT_LINESTATUS_MASK (3<<10)
80 #define PORT_LINESTATUS_KSTATE (1<<10)
81 #define PORT_RESET (1<<8)
82 #define PORT_SUSPEND (1<<7)
83 #define PORT_RESUME (1<<6)
84 #define PORT_OCC (1<<5)
85 #define PORT_OC (1<<4)
86 #define PORT_PEC (1<<3)
87 #define PORT_PE (1<<2)
88 #define PORT_CSC (1<<1)
89 #define PORT_CONNECT (1<<0)
90 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
93 #define EHCI_QH_ALIGN 64 // Can't span a 4K boundary, so increase to 64
108 #define QH_CONTROL (1 << 27)
109 #define QH_MAXPACKET_SHIFT 16
110 #define QH_MAXPACKET_MASK (0x7ff << QH_MAXPACKET_SHIFT)
111 #define QH_HEAD (1 << 15)
112 #define QH_TOGGLECONTROL (1 << 14)
113 #define QH_SPEED_SHIFT 12
114 #define QH_SPEED_MASK (0x3 << QH_SPEED_SHIFT)
115 #define QH_EP_SHIFT 8
116 #define QH_EP_MASK (0xf << QH_EP_SHIFT)
117 #define QH_DEVADDR_SHIFT 0
118 #define QH_DEVADDR_MASK (0x7f << QH_DEVADDR_SHIFT)
120 #define QH_SMASK_SHIFT 0
121 #define QH_SMASK_MASK (0xff << QH_SMASK_SHIFT)
122 #define QH_CMASK_SHIFT 8
123 #define QH_CMASK_MASK (0xff << QH_CMASK_SHIFT)
124 #define QH_HUBADDR_SHIFT 16
125 #define QH_HUBADDR_MASK (0x7f << QH_HUBADDR_SHIFT)
126 #define QH_HUBPORT_SHIFT 23
127 #define QH_HUBPORT_MASK (0x7f << QH_HUBPORT_SHIFT)
128 #define QH_MULT_SHIFT 30
129 #define QH_MULT_MASK (0x3 << QH_MULT_SHIFT)
131 #define EHCI_PTR_BITS 0x001F
132 #define EHCI_PTR_TERM 0x0001
133 #define EHCI_PTR_QH 0x0002
136 #define EHCI_QTD_ALIGN 32
146 #define QTD_TOGGLE (1 << 31)
147 #define QTD_LENGTH_SHIFT 16
148 #define QTD_LENGTH_MASK (0x7fff << QTD_LENGTH_SHIFT)
149 #define QTD_CERR_SHIFT 10
150 #define QTD_CERR_MASK (0x3 << QTD_CERR_SHIFT)
151 #define QTD_IOC (1 << 15)
152 #define QTD_PID_OUT (0x0 << 8)
153 #define QTD_PID_IN (0x1 << 8)
154 #define QTD_PID_SETUP (0x2 << 8)
155 #define QTD_STS_ACTIVE (1 << 7)
156 #define QTD_STS_HALT (1 << 6)
157 #define QTD_STS_DBE (1 << 5)
158 #define QTD_STS_BABBLE (1 << 4)
159 #define QTD_STS_XACT (1 << 3)
160 #define QTD_STS_MMF (1 << 2)
161 #define QTD_STS_STS (1 << 1)
162 #define QTD_STS_PING (1 << 0)
164 #define ehci_explen(len) (((len) << QTD_LENGTH_SHIFT) & QTD_LENGTH_MASK)
166 #define ehci_maxerr(err) (((err) << QTD_CERR_SHIFT) & QTD_CERR_MASK)
169 struct ehci_framelist {