1 // Initialize PCI devices (on emulators)
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "util.h" // dprintf
9 #include "pci.h" // pci_config_readl
10 #include "biosvar.h" // GET_EBDA
11 #include "pci_ids.h" // PCI_VENDOR_ID_INTEL
12 #include "pci_regs.h" // PCI_COMMAND
13 #include "xen.h" // usingXen
15 #define PCI_IO_INDEX_SHIFT 2
16 #define PCI_MEM_INDEX_SHIFT 12
18 #define PCI_BRIDGE_IO_MIN 0x1000
19 #define PCI_BRIDGE_MEM_MIN 0x100000
21 enum pci_region_type {
24 PCI_REGION_TYPE_PREFMEM,
25 PCI_REGION_TYPE_COUNT,
28 static const char *region_type_name[] = {
29 [ PCI_REGION_TYPE_IO ] = "io",
30 [ PCI_REGION_TYPE_MEM ] = "mem",
31 [ PCI_REGION_TYPE_PREFMEM ] = "prefmem",
34 static struct pci_bus {
36 /* pci region stats */
37 u32 count[32 - PCI_MEM_INDEX_SHIFT];
39 /* seconday bus region sizes */
41 /* pci region assignments */
42 u32 bases[32 - PCI_MEM_INDEX_SHIFT];
44 } r[PCI_REGION_TYPE_COUNT];
46 static int busses_count;
48 static void pci_bios_init_device_in_bus(int bus);
49 static void pci_bios_check_device_in_bus(int bus);
50 static void pci_bios_init_bus_bases(struct pci_bus *bus);
51 static void pci_bios_map_device_in_bus(int bus);
53 static int pci_size_to_index(u32 size, enum pci_region_type type)
55 int index = __fls(size);
56 int shift = (type == PCI_REGION_TYPE_IO) ?
57 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
65 static u32 pci_index_to_size(int index, enum pci_region_type type)
67 int shift = (type == PCI_REGION_TYPE_IO) ?
68 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
70 return 0x1 << (index + shift);
73 static enum pci_region_type pci_addr_to_type(u32 addr)
75 if (addr & PCI_BASE_ADDRESS_SPACE_IO)
76 return PCI_REGION_TYPE_IO;
77 if (addr & PCI_BASE_ADDRESS_MEM_PREFETCH)
78 return PCI_REGION_TYPE_PREFMEM;
79 return PCI_REGION_TYPE_MEM;
82 static u32 pci_size_roundup(u32 size)
84 int index = __fls(size-1)+1;
88 /* host irqs corresponding to PCI irqs A-D */
89 const u8 pci_irqs[4] = {
93 static u32 pci_bar(u16 bdf, int region_num)
95 if (region_num != PCI_ROM_SLOT) {
96 return PCI_BASE_ADDRESS_0 + region_num * 4;
99 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
100 u8 type = pci_config_readb(bdf, PCI_HEADER_TYPE);
101 type &= ~PCI_HEADER_TYPE_MULTI_FUNCTION;
102 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
105 static void pci_set_io_region_addr(u16 bdf, int region_num, u32 addr)
109 ofs = pci_bar(bdf, region_num);
111 pci_config_writel(bdf, ofs, addr);
114 /* return the global irq number corresponding to a given device irq
115 pin. We could also use the bus number to have a more precise
117 static int pci_slot_get_pirq(u16 bdf, int irq_num)
119 int slot_addend = pci_bdf_to_dev(bdf) - 1;
120 return (irq_num + slot_addend) & 3;
123 /* PIIX3/PIIX4 PCI to ISA bridge */
124 static void piix_isa_bridge_init(struct pci_device *pci, void *arg)
131 for (i = 0; i < 4; i++) {
133 /* set to trigger level */
134 elcr[irq >> 3] |= (1 << (irq & 7));
135 /* activate irq remapping in PIIX */
136 pci_config_writeb(pci->bdf, 0x60 + i, irq);
138 outb(elcr[0], 0x4d0);
139 outb(elcr[1], 0x4d1);
140 dprintf(1, "PIIX3/PIIX4 init: elcr=%02x %02x\n", elcr[0], elcr[1]);
143 static const struct pci_device_id pci_isa_bridge_tbl[] = {
144 /* PIIX3/PIIX4 PCI to ISA bridge */
145 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0,
146 piix_isa_bridge_init),
147 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
148 piix_isa_bridge_init),
153 #define PCI_IO_ALIGN 4096
154 #define PCI_IO_SHIFT 8
155 #define PCI_MEMORY_ALIGN (1UL << 20)
156 #define PCI_MEMORY_SHIFT 16
157 #define PCI_PREF_MEMORY_ALIGN (1UL << 20)
158 #define PCI_PREF_MEMORY_SHIFT 16
160 static void storage_ide_init(struct pci_device *pci, void *arg)
163 /* IDE: we map it as in ISA mode */
164 pci_set_io_region_addr(bdf, 0, PORT_ATA1_CMD_BASE);
165 pci_set_io_region_addr(bdf, 1, PORT_ATA1_CTRL_BASE);
166 pci_set_io_region_addr(bdf, 2, PORT_ATA2_CMD_BASE);
167 pci_set_io_region_addr(bdf, 3, PORT_ATA2_CTRL_BASE);
170 /* PIIX3/PIIX4 IDE */
171 static void piix_ide_init(struct pci_device *pci, void *arg)
174 pci_config_writew(bdf, 0x40, 0x8000); // enable IDE0
175 pci_config_writew(bdf, 0x42, 0x8000); // enable IDE1
178 static void pic_ibm_init(struct pci_device *pci, void *arg)
180 /* PIC, IBM, MPIC & MPIC2 */
181 pci_set_io_region_addr(pci->bdf, 0, 0x80800000 + 0x00040000);
184 static void apple_macio_init(struct pci_device *pci, void *arg)
187 pci_set_io_region_addr(pci->bdf, 0, 0x80800000);
190 static const struct pci_device_id pci_class_tbl[] = {
192 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_1,
193 PCI_CLASS_STORAGE_IDE, piix_ide_init),
194 PCI_DEVICE_CLASS(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB,
195 PCI_CLASS_STORAGE_IDE, piix_ide_init),
196 PCI_DEVICE_CLASS(PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
199 /* PIC, IBM, MIPC & MPIC2 */
200 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0x0046, PCI_CLASS_SYSTEM_PIC,
202 PCI_DEVICE_CLASS(PCI_VENDOR_ID_IBM, 0xFFFF, PCI_CLASS_SYSTEM_PIC,
206 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0017, 0xff00, apple_macio_init),
207 PCI_DEVICE_CLASS(PCI_VENDOR_ID_APPLE, 0x0022, 0xff00, apple_macio_init),
212 /* PIIX4 Power Management device (for ACPI) */
213 static void piix4_pm_init(struct pci_device *pci, void *arg)
216 // acpi sci is hardwired to 9
217 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, 9);
219 pci_config_writel(bdf, 0x40, PORT_ACPI_PM_BASE | 1);
220 pci_config_writeb(bdf, 0x80, 0x01); /* enable PM io space */
221 pci_config_writel(bdf, 0x90, PORT_SMB_BASE | 1);
222 pci_config_writeb(bdf, 0xd2, 0x09); /* enable SMBus io space */
225 static const struct pci_device_id pci_device_tbl[] = {
226 /* PIIX4 Power Management device (for ACPI) */
227 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
233 static void pci_bios_init_device(struct pci_device *pci)
238 dprintf(1, "PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x\n"
239 , pci_bdf_to_bus(bdf), pci_bdf_to_devfn(bdf)
240 , pci->vendor, pci->device);
241 pci_init_device(pci_class_tbl, pci, NULL);
243 /* enable memory mappings */
244 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
246 /* map the interrupt */
247 pin = pci_config_readb(bdf, PCI_INTERRUPT_PIN);
249 pin = pci_slot_get_pirq(bdf, pin - 1);
250 pic_irq = pci_irqs[pin];
251 pci_config_writeb(bdf, PCI_INTERRUPT_LINE, pic_irq);
254 pci_init_device(pci_device_tbl, pci, NULL);
257 static void pci_bios_init_device_in_bus(int bus)
259 struct pci_device *pci;
261 u8 pci_bus = pci_bdf_to_bus(pci->bdf);
266 pci_bios_init_device(pci);
271 pci_bios_init_bus_rec(int bus, u8 *pci_bus)
276 dprintf(1, "PCI: %s bus = 0x%x\n", __func__, bus);
278 /* prevent accidental access to unintended devices */
279 foreachbdf(bdf, bus) {
280 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
281 if (class == PCI_CLASS_BRIDGE_PCI) {
282 pci_config_writeb(bdf, PCI_SECONDARY_BUS, 255);
283 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 0);
287 foreachbdf(bdf, bus) {
288 class = pci_config_readw(bdf, PCI_CLASS_DEVICE);
289 if (class != PCI_CLASS_BRIDGE_PCI) {
292 dprintf(1, "PCI: %s bdf = 0x%x\n", __func__, bdf);
294 u8 pribus = pci_config_readb(bdf, PCI_PRIMARY_BUS);
296 dprintf(1, "PCI: primary bus = 0x%x -> 0x%x\n", pribus, bus);
297 pci_config_writeb(bdf, PCI_PRIMARY_BUS, bus);
299 dprintf(1, "PCI: primary bus = 0x%x\n", pribus);
302 u8 secbus = pci_config_readb(bdf, PCI_SECONDARY_BUS);
304 if (*pci_bus != secbus) {
305 dprintf(1, "PCI: secondary bus = 0x%x -> 0x%x\n",
308 pci_config_writeb(bdf, PCI_SECONDARY_BUS, secbus);
310 dprintf(1, "PCI: secondary bus = 0x%x\n", secbus);
313 /* set to max for access to all subordinate buses.
314 later set it to accurate value */
315 u8 subbus = pci_config_readb(bdf, PCI_SUBORDINATE_BUS);
316 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, 255);
318 pci_bios_init_bus_rec(secbus, pci_bus);
320 if (subbus != *pci_bus) {
321 dprintf(1, "PCI: subordinate bus = 0x%x -> 0x%x\n",
325 dprintf(1, "PCI: subordinate bus = 0x%x\n", subbus);
327 pci_config_writeb(bdf, PCI_SUBORDINATE_BUS, subbus);
332 pci_bios_init_bus(void)
335 pci_bios_init_bus_rec(0 /* host bus */, &pci_bus);
336 busses_count = pci_bus + 1;
339 static void pci_bios_bus_get_bar(struct pci_bus *bus, int bdf, int bar,
342 u32 ofs = pci_bar(bdf, bar);
343 u32 old = pci_config_readl(bdf, ofs);
346 if (bar == PCI_ROM_SLOT) {
347 mask = PCI_ROM_ADDRESS_MASK;
348 pci_config_writel(bdf, ofs, mask);
350 if (old & PCI_BASE_ADDRESS_SPACE_IO)
351 mask = PCI_BASE_ADDRESS_IO_MASK;
353 mask = PCI_BASE_ADDRESS_MEM_MASK;
354 pci_config_writel(bdf, ofs, ~0);
356 *val = pci_config_readl(bdf, ofs);
357 pci_config_writel(bdf, ofs, old);
358 *size = (~(*val & mask)) + 1;
361 static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size)
365 index = pci_size_to_index(size, type);
366 size = pci_index_to_size(index, type);
367 bus->r[type].count[index]++;
368 bus->r[type].sum += size;
369 if (bus->r[type].max < size)
370 bus->r[type].max = size;
373 static u32 pci_bios_bus_get_addr(struct pci_bus *bus, int type, u32 size)
377 index = pci_size_to_index(size, type);
378 addr = bus->r[type].bases[index];
379 bus->r[type].bases[index] += pci_index_to_size(index, type);
383 static void pci_bios_check_device(struct pci_bus *bus, struct pci_device *dev)
389 if (dev->class == PCI_CLASS_BRIDGE_PCI) {
390 if (dev->secondary_bus >= busses_count) {
391 /* should never trigger */
392 dprintf(1, "PCI: bus count too small (%d), skipping bus #%d\n",
393 busses_count, dev->secondary_bus);
396 struct pci_bus *s = busses + dev->secondary_bus;
397 pci_bios_check_device_in_bus(dev->secondary_bus);
398 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
399 limit = (type == PCI_REGION_TYPE_IO) ?
400 PCI_BRIDGE_IO_MIN : PCI_BRIDGE_MEM_MIN;
401 s->r[type].size = s->r[type].sum;
402 if (s->r[type].size < limit)
403 s->r[type].size = limit;
404 s->r[type].size = pci_size_roundup(s->r[type].size);
405 pci_bios_bus_reserve(bus, type, s->r[type].size);
407 dprintf(1, "PCI: secondary bus %d sizes: io %x, mem %x, prefmem %x\n",
409 s->r[PCI_REGION_TYPE_IO].size,
410 s->r[PCI_REGION_TYPE_MEM].size,
411 s->r[PCI_REGION_TYPE_PREFMEM].size);
415 for (i = 0; i < PCI_NUM_REGIONS; i++) {
417 pci_bios_bus_get_bar(bus, bdf, i, &val, &size);
421 pci_bios_bus_reserve(bus, pci_addr_to_type(val), size);
422 dev->bars[i].addr = val;
423 dev->bars[i].size = size;
424 dev->bars[i].is64 = (!(val & PCI_BASE_ADDRESS_SPACE_IO) &&
425 (val & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64);
427 if (dev->bars[i].is64) {
433 static void pci_bios_map_device(struct pci_bus *bus, struct pci_device *dev)
438 if (dev->class == PCI_CLASS_BRIDGE_PCI) {
439 if (dev->secondary_bus >= busses_count) {
442 struct pci_bus *s = busses + dev->secondary_bus;
445 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
446 s->r[type].base = pci_bios_bus_get_addr(bus, type, s->r[type].size);
448 dprintf(1, "PCI: init bases bus %d (secondary)\n", dev->secondary_bus);
449 pci_bios_init_bus_bases(s);
451 base = s->r[PCI_REGION_TYPE_IO].base;
452 limit = base + s->r[PCI_REGION_TYPE_IO].size - 1;
453 pci_config_writeb(bdf, PCI_IO_BASE, base >> PCI_IO_SHIFT);
454 pci_config_writew(bdf, PCI_IO_BASE_UPPER16, 0);
455 pci_config_writeb(bdf, PCI_IO_LIMIT, limit >> PCI_IO_SHIFT);
456 pci_config_writew(bdf, PCI_IO_LIMIT_UPPER16, 0);
458 base = s->r[PCI_REGION_TYPE_MEM].base;
459 limit = base + s->r[PCI_REGION_TYPE_MEM].size - 1;
460 pci_config_writew(bdf, PCI_MEMORY_BASE, base >> PCI_MEMORY_SHIFT);
461 pci_config_writew(bdf, PCI_MEMORY_LIMIT, limit >> PCI_MEMORY_SHIFT);
463 base = s->r[PCI_REGION_TYPE_PREFMEM].base;
464 limit = base + s->r[PCI_REGION_TYPE_PREFMEM].size - 1;
465 pci_config_writew(bdf, PCI_PREF_MEMORY_BASE, base >> PCI_PREF_MEMORY_SHIFT);
466 pci_config_writew(bdf, PCI_PREF_MEMORY_LIMIT, limit >> PCI_PREF_MEMORY_SHIFT);
467 pci_config_writel(bdf, PCI_PREF_BASE_UPPER32, 0);
468 pci_config_writel(bdf, PCI_PREF_LIMIT_UPPER32, 0);
470 pci_bios_map_device_in_bus(dev->secondary_bus);
474 for (i = 0; i < PCI_NUM_REGIONS; i++) {
476 if (dev->bars[i].addr == 0) {
480 addr = pci_bios_bus_get_addr(bus, pci_addr_to_type(dev->bars[i].addr),
482 dprintf(1, " bar %d, addr %x, size %x [%s]\n",
483 i, addr, dev->bars[i].size,
484 dev->bars[i].addr & PCI_BASE_ADDRESS_SPACE_IO ? "io" : "mem");
485 pci_set_io_region_addr(bdf, i, addr);
487 if (dev->bars[i].is64) {
493 static void pci_bios_check_device_in_bus(int bus)
495 struct pci_device *pci;
497 dprintf(1, "PCI: check devices bus %d\n", bus);
499 if (pci_bdf_to_bus(pci->bdf) != bus)
501 pci_bios_check_device(&busses[bus], pci);
505 static void pci_bios_map_device_in_bus(int bus)
507 struct pci_device *pci;
510 if (pci_bdf_to_bus(pci->bdf) != bus)
512 dprintf(1, "PCI: map device bus %d, bfd 0x%x\n", bus, pci->bdf);
513 pci_bios_map_device(&busses[bus], pci);
517 static void pci_bios_init_bus_bases(struct pci_bus *bus)
519 u32 base, newbase, size;
522 for (type = 0; type < PCI_REGION_TYPE_COUNT; type++) {
523 dprintf(1, " type %s max %x sum %x base %x\n", region_type_name[type],
524 bus->r[type].max, bus->r[type].sum, bus->r[type].base);
525 base = bus->r[type].base;
526 for (i = ARRAY_SIZE(bus->r[type].count)-1; i >= 0; i--) {
527 size = pci_index_to_size(i, type);
528 if (!bus->r[type].count[i])
530 newbase = base + size * bus->r[type].count[i];
531 dprintf(1, " size %8x: %d bar(s), %8x -> %8x\n",
532 size, bus->r[type].count[i], base, newbase - 1);
533 bus->r[type].bases[i] = base;
539 #define ROOT_BASE(top, sum, max) ALIGN_DOWN((top)-(sum),(max) ?: 1)
541 static int pci_bios_init_root_regions(u32 start, u32 end)
543 struct pci_bus *bus = &busses[0];
545 bus->r[PCI_REGION_TYPE_IO].base = 0xc000;
547 if (bus->r[PCI_REGION_TYPE_MEM].sum < bus->r[PCI_REGION_TYPE_PREFMEM].sum) {
548 bus->r[PCI_REGION_TYPE_MEM].base =
550 bus->r[PCI_REGION_TYPE_MEM].sum,
551 bus->r[PCI_REGION_TYPE_MEM].max);
552 bus->r[PCI_REGION_TYPE_PREFMEM].base =
553 ROOT_BASE(bus->r[PCI_REGION_TYPE_MEM].base,
554 bus->r[PCI_REGION_TYPE_PREFMEM].sum,
555 bus->r[PCI_REGION_TYPE_PREFMEM].max);
556 if (bus->r[PCI_REGION_TYPE_PREFMEM].base >= start) {
560 bus->r[PCI_REGION_TYPE_PREFMEM].base =
562 bus->r[PCI_REGION_TYPE_PREFMEM].sum,
563 bus->r[PCI_REGION_TYPE_PREFMEM].max);
564 bus->r[PCI_REGION_TYPE_MEM].base =
565 ROOT_BASE(bus->r[PCI_REGION_TYPE_PREFMEM].base,
566 bus->r[PCI_REGION_TYPE_MEM].sum,
567 bus->r[PCI_REGION_TYPE_MEM].max);
568 if (bus->r[PCI_REGION_TYPE_MEM].base >= start) {
578 if (CONFIG_COREBOOT || usingXen()) {
579 // PCI setup already done by coreboot or Xen - just do probe.
584 dprintf(3, "pci setup\n");
586 u32 start = BUILD_PCIMEM_START;
587 u32 end = BUILD_PCIMEM_END;
589 dprintf(1, "=== PCI bus & bridge init ===\n");
590 if (pci_probe_host() != 0) {
595 dprintf(1, "=== PCI device probing ===\n");
598 dprintf(1, "=== PCI new allocation pass #1 ===\n");
599 busses = malloc_tmp(sizeof(*busses) * busses_count);
600 memset(busses, 0, sizeof(*busses) * busses_count);
601 pci_bios_check_device_in_bus(0 /* host bus */);
602 if (pci_bios_init_root_regions(start, end) != 0) {
603 panic("PCI: out of address space\n");
606 dprintf(1, "=== PCI new allocation pass #2 ===\n");
607 dprintf(1, "PCI: init bases bus 0 (primary)\n");
608 pci_bios_init_bus_bases(&busses[0]);
609 pci_bios_map_device_in_bus(0 /* host bus */);
611 pci_bios_init_device_in_bus(0 /* host bus */);
613 struct pci_device *pci;
615 pci_init_device(pci_isa_bridge_tbl, pci, NULL);