1 // Definitions for X86 IO port access.
3 // Copyright (C) 2008 Kevin O'Connor <kevin@koconnor.net>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
9 #define PORT_DMA_ADDR_2 0x0004
10 #define PORT_DMA_CNT_2 0x0005
11 #define PORT_DMA1_MASK_REG 0x000a
12 #define PORT_DMA1_MODE_REG 0x000b
13 #define PORT_DMA1_CLEAR_FF_REG 0x000c
14 #define PORT_DMA1_MASTER_CLEAR 0x000d
15 #define PORT_PIC1_CMD 0x0020
16 #define PORT_PIC1_DATA 0x0021
17 #define PORT_PIT_COUNTER0 0x0040
18 #define PORT_PIT_COUNTER1 0x0041
19 #define PORT_PIT_COUNTER2 0x0042
20 #define PORT_PIT_MODE 0x0043
21 #define PORT_PS2_DATA 0x0060
22 #define PORT_PS2_CTRLB 0x0061
23 #define PORT_PS2_STATUS 0x0064
24 #define PORT_CMOS_INDEX 0x0070
25 #define PORT_CMOS_DATA 0x0071
26 #define PORT_DIAG 0x0080
27 #define PORT_DMA_PAGE_2 0x0081
28 #define PORT_A20 0x0092
29 #define PORT_PIC2_CMD 0x00a0
30 #define PORT_PIC2_DATA 0x00a1
31 #define PORT_SMI_CMD 0x00b2
32 #define PORT_SMI_STATUS 0x00b3
33 #define PORT_DMA2_MASK_REG 0x00d4
34 #define PORT_DMA2_MODE_REG 0x00d6
35 #define PORT_DMA2_MASTER_CLEAR 0x00da
36 #define PORT_MATH_CLEAR 0x00f0
37 #define PORT_ATA2_CMD_BASE 0x0170
38 #define PORT_ATA1_CMD_BASE 0x01f0
39 #define PORT_LPT2 0x0278
40 #define PORT_SERIAL4 0x02e8
41 #define PORT_SERIAL2 0x02f8
42 #define PORT_ATA2_CTRL_BASE 0x0374
43 #define PORT_LPT1 0x0378
44 #define PORT_SERIAL3 0x03e8
45 #define PORT_ATA1_CTRL_BASE 0x03f4
46 #define PORT_FD_BASE 0x03f0
47 #define PORT_FD_DOR 0x03f2
48 #define PORT_FD_STATUS 0x03f4
49 #define PORT_FD_DATA 0x03f5
50 #define PORT_HD_DATA 0x03f6
51 #define PORT_FD_DIR 0x03f7
52 #define PORT_SERIAL1 0x03f8
53 #define PORT_PCI_CMD 0x0cf8
54 #define PORT_PCI_REBOOT 0x0cf9
55 #define PORT_PCI_DATA 0x0cfc
56 #define PORT_BIOS_DEBUG 0x0402
57 #define PORT_QEMU_CFG_CTL 0x0510
58 #define PORT_QEMU_CFG_DATA 0x0511
59 #define PORT_ACPI_PM_BASE 0xb000
60 #define PORT_SMB_BASE 0xb100
61 #define PORT_BIOS_APM 0x8900
63 // Serial port offsets
74 #define A20_ENABLE_BIT 0x02
76 // PORT_CMOS_INDEX nmi disable bit
77 #define NMI_DISABLE_BIT 0x80
81 #include "types.h" // u8
83 static inline void outb(u8 value, u16 port) {
84 __asm__ __volatile__("outb %b0, %w1" : : "a"(value), "Nd"(port));
86 static inline void outw(u16 value, u16 port) {
87 __asm__ __volatile__("outw %w0, %w1" : : "a"(value), "Nd"(port));
89 static inline void outl(u32 value, u16 port) {
90 __asm__ __volatile__("outl %0, %w1" : : "a"(value), "Nd"(port));
92 static inline u8 inb(u16 port) {
94 __asm__ __volatile__("inb %w1, %b0" : "=a"(value) : "Nd"(port));
97 static inline u16 inw(u16 port) {
99 __asm__ __volatile__("inw %w1, %w0" : "=a"(value) : "Nd"(port));
102 static inline u32 inl(u16 port) {
104 __asm__ __volatile__("inl %w1, %0" : "=a"(value) : "Nd"(port));
108 static inline void insb(u16 port, u8 *data, u32 count) {
109 asm volatile("rep insb (%%dx), %%es:(%%edi)"
110 : "+c"(count), "+D"(data) : "d"(port) : "memory");
112 static inline void insw(u16 port, u16 *data, u32 count) {
113 asm volatile("rep insw (%%dx), %%es:(%%edi)"
114 : "+c"(count), "+D"(data) : "d"(port) : "memory");
116 static inline void insl(u16 port, u32 *data, u32 count) {
117 asm volatile("rep insl (%%dx), %%es:(%%edi)"
118 : "+c"(count), "+D"(data) : "d"(port) : "memory");
120 // XXX - outs not limited to es segment
121 static inline void outsb(u16 port, u8 *data, u32 count) {
122 asm volatile("rep outsb %%es:(%%esi), (%%dx)"
123 : "+c"(count), "+S"(data) : "d"(port) : "memory");
125 static inline void outsw(u16 port, u16 *data, u32 count) {
126 asm volatile("rep outsw %%es:(%%esi), (%%dx)"
127 : "+c"(count), "+S"(data) : "d"(port) : "memory");
129 static inline void outsl(u16 port, u32 *data, u32 count) {
130 asm volatile("rep outsl %%es:(%%esi), (%%dx)"
131 : "+c"(count), "+S"(data) : "d"(port) : "memory");
134 #endif // !__ASSEMBLY__