29 struct pci_device *pci_tmp;
38 struct sata_cmd_fis fis;
59 u8 dsfis[0x1c]; /* dma setup */
61 u8 psfis[0x14]; /* pio setup */
63 u8 rfis[0x14]; /* d2h register */
65 u8 sdbfis[0x08]; /* set device bits */
66 u8 ufis[0x40]; /* unknown */
72 struct ahci_ctrl_s *ctrl;
73 struct ahci_list_s *list;
74 struct ahci_fis_s *fis;
75 struct ahci_cmd_s *cmd;
82 void ahci_setup(void);
83 int process_ahci_op(struct disk_op_s *op);
84 int ahci_cmd_data(struct disk_op_s *op, void *cdbcmd, u16 blocksize);
86 #define AHCI_IRQ_ON_SG (1 << 31)
87 #define AHCI_CMD_ATAPI (1 << 5)
88 #define AHCI_CMD_WRITE (1 << 6)
89 #define AHCI_CMD_PREFETCH (1 << 7)
90 #define AHCI_CMD_RESET (1 << 8)
91 #define AHCI_CMD_CLR_BUSY (1 << 10)
93 #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
94 #define RX_FIS_SDB 0x58 /* offset of SDB FIS data */
95 #define RX_FIS_UNK 0x60 /* offset of Unknown FIS data */
97 /* global controller registers */
98 #define HOST_CAP 0x00 /* host capabilities */
99 #define HOST_CTL 0x04 /* global host control */
100 #define HOST_IRQ_STAT 0x08 /* interrupt status */
101 #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
102 #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
105 #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
106 #define HOST_CTL_IRQ_EN (1 << 1) /* global IRQ enable */
107 #define HOST_CTL_AHCI_EN (1 << 31) /* AHCI enabled */
110 #define HOST_CAP_SSC (1 << 14) /* Slumber capable */
111 #define HOST_CAP_AHCI (1 << 18) /* AHCI only */
112 #define HOST_CAP_CLO (1 << 24) /* Command List Override support */
113 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
114 #define HOST_CAP_NCQ (1 << 30) /* Native Command Queueing */
115 #define HOST_CAP_64 (1 << 31) /* PCI DAC (64-bit DMA) support */
117 /* registers for each SATA port */
118 #define PORT_LST_ADDR 0x00 /* command list DMA addr */
119 #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
120 #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
121 #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
122 #define PORT_IRQ_STAT 0x10 /* interrupt status */
123 #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
124 #define PORT_CMD 0x18 /* port command */
125 #define PORT_TFDATA 0x20 /* taskfile data */
126 #define PORT_SIG 0x24 /* device TF signature */
127 #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
128 #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
129 #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
130 #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
131 #define PORT_CMD_ISSUE 0x38 /* command issue */
132 #define PORT_RESERVED 0x3c /* reserved */
134 /* PORT_IRQ_{STAT,MASK} bits */
135 #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
136 #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
137 #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
138 #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
139 #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
140 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
141 #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
142 #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
144 #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
145 #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
146 #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
147 #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
148 #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
149 #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
150 #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
151 #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
152 #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
154 #define PORT_IRQ_FREEZE (PORT_IRQ_HBUS_ERR | PORT_IRQ_IF_ERR | \
155 PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY | \
157 #define PORT_IRQ_ERROR (PORT_IRQ_FREEZE | PORT_IRQ_TF_ERR | \
158 PORT_IRQ_HBUS_DATA_ERR)
159 #define DEF_PORT_IRQ (PORT_IRQ_ERROR | PORT_IRQ_SG_DONE | \
160 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS | \
161 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS)
164 #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
165 #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
166 #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
167 #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
168 #define PORT_CMD_CLO (1 << 3) /* Command list override */
169 #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
170 #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
171 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
173 #define PORT_CMD_ICC_MASK (0xf << 28) /* i/f ICC state mask */
174 #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
175 #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
176 #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
178 #define PORT_IRQ_STAT_DHRS (1 << 0) /* Device to Host Register FIS */
179 #define PORT_IRQ_STAT_PSS (1 << 1) /* PIO Setup FIS */
180 #define PORT_IRQ_STAT_DSS (1 << 2) /* DMA Setup FIS */
181 #define PORT_IRQ_STAT_SDBS (1 << 3) /* Set Device Bits */
182 #define PORT_IRQ_STAT_UFS (1 << 4) /* Unknown FIS */
183 #define PORT_IRQ_STAT_DPS (1 << 5) /* Descriptor Processed */
184 #define PORT_IRQ_STAT_PCS (1 << 6) /* Port Connect Change Status */
185 #define PORT_IRQ_STAT_DMPS (1 << 7) /* Device Mechanical Presence
187 #define PORT_IRQ_STAT_PRCS (1 << 22) /* File Ready Status */
188 #define PORT_IRQ_STAT_IPMS (1 << 23) /* Incorrect Port Multiplier
190 #define PORT_IRQ_STAT_OFS (1 << 24) /* Overflow Status */
191 #define PORT_IRQ_STAT_INFS (1 << 26) /* Interface Non-Fatal Error
193 #define PORT_IRQ_STAT_IFS (1 << 27) /* Interface Fatal Error */
194 #define PORT_IRQ_STAT_HBDS (1 << 28) /* Host Bus Data Error Status */
195 #define PORT_IRQ_STAT_HBFS (1 << 29) /* Host Bus Fatal Error Status */
196 #define PORT_IRQ_STAT_TFES (1 << 30) /* Task File Error Status */
197 #define PORT_IRQ_STAT_CPDS (1 << 31) /* Code Port Detect Status */