From 3ee4361bc89ee16b21fb3f4d0d5809ca70886406 Mon Sep 17 00:00:00 2001 From: Alexander Sadovskiy Date: Tue, 20 Dec 2011 20:28:42 +0400 Subject: [PATCH 33/33] Minor fixes found during MSI-X debugging apic.c - small typo fixes pci_passthrough.c - added #ifdef to compile palacios w/o IRQ_BALANCE pci_msi_router.c - fixed checking if vector was masked + lots of useful debug messages (commented out because they are too frequent and only needed in deep debugging of passthrough) --- palacios/src/devices/apic.c | 4 ++-- palacios/src/devices/pci_msi_router.c | 15 ++++++++++----- palacios/src/devices/pci_passthrough.c | 12 ++++++++++-- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/palacios/src/devices/apic.c b/palacios/src/devices/apic.c index f28046e..655289a 100644 --- a/palacios/src/devices/apic.c +++ b/palacios/src/devices/apic.c @@ -268,7 +268,7 @@ struct apic_dev_state { static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data); static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data); -// No lcoking done +// No locking done static void init_apic_state(struct apic_state * apic, uint32_t id) { apic->base_addr = DEFAULT_BASE_ADDR; @@ -564,7 +564,7 @@ static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_t // interrupt is masked, don't send if (masked == 1) { - PrintDebug("apic %u: core ?: Inerrupt is masked\n", apic->lapic_id.val); + PrintDebug("apic %u: core ?: Interrupt is masked\n", apic->lapic_id.val); return 0; } diff --git a/palacios/src/devices/pci_msi_router.c b/palacios/src/devices/pci_msi_router.c index d2e494e..d50c37d 100644 --- a/palacios/src/devices/pci_msi_router.c +++ b/palacios/src/devices/pci_msi_router.c @@ -543,7 +543,9 @@ int v3_msix_memory_write(struct pci_device *dev, addr_t guest_addr, void * src, struct msix_tbl_entry *table = &mx->table[table_num]; union msix_vec_ctl old_ctl = table->ctl; while(length) { - if (table_offset != 12) PrintDebug("Device %s: MSI-X table %d, offset %d write (value %08x).\n", dev->name, table_num, table_offset, *(uint32_t*)src); + if (table_offset != 12) // conditional due to so many mask/unmask writes + PrintDebug("Device %s: MSI-X table %d, offset %d write (value %08x).\n", + dev->name, table_num, table_offset, *(uint32_t*)src); switch(table_offset) { case 0: // message address table->address_lo = *(union msi_msg_address*)src; @@ -566,21 +568,24 @@ int v3_msix_memory_write(struct pci_device *dev, addr_t guest_addr, void * src, PrintError("Impossible MSI-X table entry offset %d!\n", table_offset); return -1; } - if(table_offset != 12 && !table->ctl.mask) { + /*if(table_offset != 12 && !table->ctl.mask) { PrintError("Writing to MSI-X table while vector is enabled and not masked!\n"); return -1; - } + }*/ // Doing such things looks common for linux.. length -= 4; table_offset += 4; src = (void*)((addr_t)src + 4); } if(old_ctl.mask && !table->ctl.mask) { // unmasked right now - //PrintDebug("Device %s: MSI-X interrupt %x unmasked now!\n", dev->name, table->data.vector); + /* PrintDebug("Device %s: MSI-X interrupt %x unmasked and %s now!\n", + dev->name, table->data.vector, c->enable ? "enabled" : "disabled"); */ if(msi_check_msg_address_and_data(&table->address_lo, &table->data) != 0) return -1; mx->vector_to_entry[table->data.vector] = table_num; - } else if(!old_ctl.mask) { + } else if(!old_ctl.mask && table->ctl.mask) { // masked right now + /* PrintDebug("Device %s: MSI-X interrupt %x masked now!\n", + dev->name, table->data.vector); */ mx->vector_to_entry[table->data.vector] = -1; state->vector_to_index[table->data.vector] = -1; } diff --git a/palacios/src/devices/pci_passthrough.c b/palacios/src/devices/pci_passthrough.c index 456aa77..07bbff3 100644 --- a/palacios/src/devices/pci_passthrough.c +++ b/palacios/src/devices/pci_passthrough.c @@ -970,6 +970,9 @@ static int cfg_msi_passthrough_capability_read(struct vm_device *dev, uint_t reg } } + /* PrintDebug("MSI CFG READ device %s: Read from %x reg, len %d, value %08x (addr %08x)\n", + state->name, reg_num, length, *(uint32_t *)ptr, pci_addr); */ + if(status) { PrintError("MSI PT device %s: Read of MSI capability failed.\n", dev->name); return status; @@ -987,6 +990,9 @@ static int cfg_msi_passthrough_capability_write(struct vm_device *dev, uint_t re union msi_msg_data *data = state->msi.m.msg_data; union msi_control *c = state->msi.m.control; + /* PrintDebug("MSI CFG WRITE device %s: Update to %x reg, len %d, value %08x (addr %08x)\n", + state->name, reg_num, length, *(uint32_t *)&state->pci_dev->config_space[reg_num], pci_addr); */ + // copy guest data. it will be returned to guest when it reads. if(reg_num == MSI_CAP_DATA(msi_cap, c->is_64bit_cap)) state->msi.m.msg_data_orig = *data; @@ -1230,10 +1236,10 @@ static int msix_memory_write(struct guest_info * core, addr_t guest_addr, void * PrintError("Impossible MSI-X table entry offset %d!\n", table_offset); return -1; } - if(c->enable && !c->func_mask && table_offset != 12 && !table->ctl.mask) { + /*if(c->enable && !c->func_mask && table_offset != 12 && !table->ctl.mask) { PrintError("Writing to MSI-X table while vector is enabled and not masked!\n"); return -1; - } + }*/ // Doing such things looks common for linux.. length -= 4; table_offset += 4; src = (void*)((addr_t)src + 4); @@ -1778,6 +1784,7 @@ static int setup_virt_pci_dev(struct v3_vm_info * vm_info, struct vm_device * de V3_ASSERT(devno >= 0 && devno < 32); } +#ifdef V3_CONFIG_IRQ_BALANCE PrintDebug("Checking irq_balance...\n"); if (v3_cfg_subtree(cfg, "irq_balance")) { PrintDebug("Do irq balance...\n"); @@ -1787,6 +1794,7 @@ static int setup_virt_pci_dev(struct v3_vm_info * vm_info, struct vm_device * de } } +#endif // V3_CONFIG_IRQ_BALANCE pci_dev = v3_pci_register_passthrough_device(state->pci_bus, state->real_hdr.header_type, -- 1.7.5.4