From ced6b6b53cfd87b23facc93509305d17976d3f86 Mon Sep 17 00:00:00 2001 From: Alexander Sadovskiy Date: Wed, 30 Nov 2011 19:35:11 +0400 Subject: [PATCH 27/32] Patches for making progress on ProLiant node vmx_ctrl_regs.c - just a fix of one small typo vmm_paging.c - enabled support of 1GB guest pages, it was planned and almost written by palacios developers but disabled. io_apic.c - ported patch 4dd1b9b1f155688a8196c1bc9f32f74275511718 from palacios-1.3 (Corrected delivery of PIT interrupts via the IOAPIC), although, it didn't help on this ProLiant. --- palacios/src/devices/io_apic.c | 14 +++++++++++++- palacios/src/palacios/vmm_paging.c | 16 ++++++++-------- palacios/src/palacios/vmx_ctrl_regs.c | 2 +- 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/palacios/src/devices/io_apic.c b/palacios/src/devices/io_apic.c index 47b8c63..dd861cf 100644 --- a/palacios/src/devices/io_apic.c +++ b/palacios/src/devices/io_apic.c @@ -267,10 +267,22 @@ static int ioapic_raise_irq(struct v3_vm_info * vm, void * private_data, struct struct io_apic_state * ioapic = (struct io_apic_state *)(private_data); struct redir_tbl_entry * irq_entry = NULL; int irq = irq_data.irq; + if (irq==0) { + // IRQ 0 being raised, in the Palacios context, means the PIT + // However, the convention is that it is the PIC that is connected + // to PIN 0 of the IOAPIC and the PIT is connected to pin 2 + // Hence we convert this to the relevant pin. In the future, + // the PIC may signal to the IOAPIC in a different path. + // Yes, this is kind of hideous, but it is needed to have the + // PIT correctly show up via the IOAPIC + irq=2; + } // check whether this IRQ can be processed by IOAPIC - if(irq_data.flags.valid && !irq_data.flags.uses_irqline) + if(irq_data.flags.valid && !irq_data.flags.uses_irqline) { + PrintError("ioapic %u: IRQ %d cannot be processed\n", ioapic->ioapic_id.id, irq); return -1; + } if (irq > 24) { PrintDebug("ioapic %u: IRQ out of range of IO APIC\n", ioapic->ioapic_id.id); diff --git a/palacios/src/palacios/vmm_paging.c b/palacios/src/palacios/vmm_paging.c index 972c800..9c2a30e 100644 --- a/palacios/src/palacios/vmm_paging.c +++ b/palacios/src/palacios/vmm_paging.c @@ -651,17 +651,17 @@ static pt_entry_type_t pml4e64_lookup(pml4e64_t * pml, addr_t addr, addr_t * ent static pt_entry_type_t pdpe64_lookup(pdpe64_t * pdp, addr_t addr, addr_t * entry) { pdpe64_t * pdpe_entry = &(pdp[PDPE64_INDEX(addr)]); - + if (!pdpe_entry->present) { - *entry = 0; - return PT_ENTRY_NOT_PRESENT; + *entry = 0; + return PT_ENTRY_NOT_PRESENT; } else if (pdpe_entry->large_page) { - PrintError("1 Gigabyte pages not supported\n"); - V3_ASSERT(0); - return -1; + pdpe64_1GB_t * large_pdpe = (pdpe64_1GB_t *)pdpe_entry; + *entry = BASE_TO_PAGE_ADDR_1GB(large_pdpe->page_base_addr); + return PT_ENTRY_LARGE_PAGE; } else { - *entry = BASE_TO_PAGE_ADDR(pdpe_entry->pd_base_addr); - return PT_ENTRY_PAGE; + *entry = BASE_TO_PAGE_ADDR(pdpe_entry->pd_base_addr); + return PT_ENTRY_PAGE; } } diff --git a/palacios/src/palacios/vmx_ctrl_regs.c b/palacios/src/palacios/vmx_ctrl_regs.c index 419c258..e792d55 100644 --- a/palacios/src/palacios/vmx_ctrl_regs.c +++ b/palacios/src/palacios/vmx_ctrl_regs.c @@ -207,7 +207,7 @@ static int handle_mov_to_cr0(struct guest_info * info, v3_reg_t * new_cr0, struc uint_t paging_transition = 0; PrintDebug("VCPU[%d]: Old shadow CR0: 0x%x, New shadow CR0: 0x%x, Guest CR0: 0x%x\n", - info->vcpu, *(uint32_t *)shdw_cr0, (uint32_t)*new_cr0, *(uint32_t *)guest_cr0); + info->vcpu_id, *(uint32_t *)shdw_cr0, (uint32_t)*new_cr0, *(uint32_t *)guest_cr0); /* First of all we check if CR0.PE (protected mode enabled) was changed. * If it's not UG mode, then we have to call VMXAssist, -- 1.7.5.4